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IGLOO系列IC芯片解密-ACTEL系列芯片解密

来源:龙人计算机研究所 作者:站长 时间:2010-07-09 14:36:22

      ACTEL系列IC芯片解密是目前芯片解密行业的高难度IC解密系列,该系列芯片的加密性极高,解密难度极大,特别是ACTEL公司新推出的ProASIC3系列等典型FPGA芯片系列,大部分型号目前在国内外均无破解先例。
  针对ACTEL系列高难度IC芯片解密,龙人也专门组织了高级解密工程师进行攻关研究,目前来说,技术攻关已经取得阶段性进展,部分高难度芯片的解密方案已经正式推出,而且针对多种高难度解密芯片,工程师也可以提供方案开发服务。
  提醒广大客户,ACTEL系列芯片解密由于难度极大,解密费用相对较高,解密周期较长,如果客户确实有解密需求,可以先提供相关期间给我们进行分析与测试,而且需要做好相关的预算,并考虑到风险性的存在。
Features and Benefits
Low Power
• 1.2 V to 1.5 V Core Voltage Support for Low Power
• Supports Single-Voltage System Operation
• 5 μW Power Consumption in Flash*Freeze Mode
• Low-Power Active FPGA Operation
• Flash*Freeze Technology Enables Ultra-Low Power
Consumption while Maintaining FPGA Content
• Easy Entry to / Exit from Ultra-Low-Power Flash*Freeze Mode
High Capacity
• 15 k to 1 Million System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal, Flash-Based CMOS Process
• Live-at-Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design When Powered Off
• 250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System
Performance
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption (except ARM®-enabled IGLOO®
devices) via JTAG (IEEE 1532–compliant)†
• FlashLock® to Secure FPGA Contents
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)
Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X†, and
LVCMOS 2.5 V / 5.0 V Input†
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and MLVDS
(AGL250 and above)
• Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
• Wide Range Power Supply Voltage Support per JESD8-12,
Allowing I/Os to Operate from 1.14 V to 1.575 V
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold-Sparing I/Os‡
• Programmable Output Slew Rate† and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the IGLOO Family
Clock Conditioning Circuit (CCC) and PLL†
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase Shift, Multiply/Divide, Delay
Capabilities, and External Feedback
• Wide Input Frequency Range (1.5 MHz up to 250 MHz)
Embedded Memory
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit† RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
• True Dual-Port SRAM (except ×18)†
ARM Processor Support in IGLOO FPGAs
• M1 IGLOO Devices—Cortex™-M1 Soft Processor Available
with or without Debug
 
AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000 AGLE600 
AGLE3000 AGLN010 AGLN015 AGLN020 AGLN0301 AGLN060 AGLN125
AGLN250 AGLP030 AGLP060 AGLP125
 
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